Samsung Provides One-Stop Foundry Design Environment…
Samsung Provides One-Stop Foundry Design Environment with the Launch of ‘SAFE™ Cloud Design Platform. Samsung showcases the first cloud-based chip design platform in partnership with Rescale Fabless customers can use diverse EDA tools with flexible computing power.
Samsung Electronics, a world leader in advanced semiconductor technology, today announced the launch of ‘Samsung Advanced Foundry Ecosystem (SAFE™) Cloud Design Platform (CDP)’ for fabless customers, in collaboration with Rescale, a leader in high performance computing (HPC) applications in the cloud.
The key highlight feature of Samsung foundry’s first SAFE™ Cloud Design Platform is that it provides a virtual environment to design chips in the cloud. By accessing this platform through the cloud, customers can immediately start designing at anytime and anywhere.
To maximize customers’ design convenience, SAFE™ CDP supports a very secure design condition that has verified with cloud companies. In addition, customers can utilize various Electronic Design Automation (EDA) tools offered by multiple vendors such as Ansys, Cadence, Mentor, a Siemens business and Synopsys.
Gaonchips, one of Samsung Foundry’s Design Solution Partners, has already tested the SAFE™ CDP on its 14nm automotive project using Cadence’s Innovus Implementation System and has successfully reduced its design run-time by 30 percent compared to current on-premise execution.
“We expect that our innovative design platform co-developed in partnership with Rescale will play a crucial role for the fabless industry as it evolves into efficient cloud-based design environment,” said Jae-hong Park, executive vice president of Foundry Design Platform Development at Samsung Electronics. “We remain committed to our efforts to bolster the SAFE™ ecosystem and will continue to collaborate with our SAFE™ partners on developing innovative programs that will help deliver ease of use and greater design efficiency for customers.”
As designs move to advanced nodes and as transistor scaling occurs at each node, chip designs become more complex and computing power required for these designs have increased significantly, resulting in greater overhead time and cost to customers.
By adopting CDP, customers can reduce the burden of building their own server infrastructure, while flexibly utilizing additional computing power required for chip design and verification. Furthermore, they can take full advantage of Samsung’s diverse foundry ecosystem which includes EDA, intellectual property (IP), cloud, and design services offered by reputable partners.
“We are excited to be a partner of Samsung Foundry SAFE™ ecosystem,” said Joris Poort, founder and CEO of Rescale. “We share a common vision of a global design cloud platform that efficiently supports a broad ecosystem of technologies and services for EDA customers worldwide.”
To actively respond to the latest technology trends and lower the design barrier for developing competitive SoCs, Samsung launched the SAFE™ program in early 2018 and held the first SAFE™ Forum in the United States last year.
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